Recent years have seen many research and development activities to manufacture OLED displays, FEDs, and other current-driven light-emitting devices. Especially, the OLED display is the focus of attention in view of possible applications in mobile phones, PDAs (personal digital assistants), and like mobile devices, to exploit its low voltage/low power consumption.
FIG. 39 shows the circuit structure of an OLED pixel disclosed in Published Japanese Translation of PCT Application 2002-514320 (Tokuhyo 2002-514320; published on Oct. 29, 1998).
A pixel circuit 300 in FIG. 39 includes four p-type TFTs (thin film transistors) 360, 365, 370, 375, two capacitors 350, 355, and an OLED 380. The TFTs 365, 375 and OLED 380 are connected in series between a power supply line 390 and a common cathode (GND line). The capacitor 350 and switching TFT 360 are connected in series between the gate of the driver TFT 365 and a data line 310. The switching TFT 370 is present between the gate and drain of the driver TFT 365. The capacitor 355 is present between the gate and source of the driver TFT 365. The gates of the TFTs 360, 370, 375 are connected respectively to a select line 320, an auto-zero line 330, and a lighting line 340.
In this pixel circuit 300, the auto-zero line 330 and the lighting line 340 go LOW in the first period. This turns on the switching TFTs 370, 375, placing the drain and gate of the driver TFT 365 at the same potential. The driver TFT 365 is therefore turned on, allowing a current flow from the driver TFT 365 to the OLED 380.
In this condition, the data line 310 is fed with reference voltage, and the select line 320 is set to LOW, which in turn keeps one of terminals of the capacitor 350 which connects to the TFT 360 at reference voltage.
In the second period, the lighting line 340 is set to HIGH, turning off the TFT 375.
The gate voltage of the driver TFT 365 then gradually increases. As the gate voltage reaches a value (+VDD+Vth) corresponding to the threshold voltage Vth of the driver TFT 365 (Vth<0), the driver TFT 365 is turned off.
In the third period, the auto-zero line 330 is set to HIGH, turning off the switching TFT 370. Thus, the capacitor 350 holds the difference between its gate voltage and the reference voltage.
In other words, the gate voltage of the driver TFT 365 is equal to a value (+VDD+Vth) corresponding to the threshold voltage (Vth) when the reference voltage is on the data line 310. If the voltage on the data line 310 changes from the reference voltage, a current in accordance with the change needs to flow through the driver TFT 365, regardless of the threshold voltage of the driver TFT 365.
To this end, the voltage on the data line 310 is changed by that desired amount. The select line is set to HIGH, turning off the switching TFT 360. The capacitor 355 maintains the gate voltage of the driver TFT 365. This ends a select period for the pixel.
The use of the pixel circuit in FIG. 39 in this manner enables the current output level of the driver TFT 365 to the OLED 380 to be specified regardless of the threshold voltage of the driver TFT 365.
FIG. 40 shows the circuit structure of another OLED pixel disclosed in IDW '03, pp. 535-538 (workshops held on Dec. 3, 2003).
A pixel circuit in FIG. 40 includes six p-type TFTs M1 to M6, a capacitor C1, and an OLED. The TFTs M5, M1, M6 and the OLED are connected in series between a power supply line VDD and a common cathode (GND line). The switching TFT M3 is present between the gate and drain of the driver TFT M1. The capacitor C1 is present between the gate of the driver TFT M1 and the power supply line VDD. The switching TFT M4 is present between the gate of the driver TFT M1 and an electric potential line VI. The switching TFT M2 is present between the source of the driver TFT M1 and a data line data[m].
The gates of the TFTs M5, M6 are connected to a control line em[n]. The gates of the TFTs M2, M3 are connected a gate line scan[n]. The gate of the TFT M4 is connected to a gate line scan[n−1].
In this pixel structure, the control line em[n] is set to HIGH in the first period, turning off the switching TFTs M5, M6. Further, the gate line scan[n−1] goes LOW, turning on the switching TFT M4. The gate line scan[n] is HIGH, keeping the switching TFTs M2, M3 turned off.
This makes the gate voltage of the driver TFT M1 equal to the voltage VI. This voltage VI can be specified to such a value that it turns on the driver TFT M1.
In the second period, the gate line scan[n−1] is set to HIGH, turning off the switching TFT M4. Further, the gate line scan[n] is set to LOW, turning on the switching TFTs M2, M3.
This short-circuits the source of the driver TFT M1 to the data line data[m], allowing a current flow from the data line data[m] to the gate of the driver TFT M1. The gate voltage of the driver TFT M1 is equal to Vda+Vth, or higher than the voltage, Vda, on the data line data[m] by a threshold voltage Vth (Vth<0).
In the following third period, the gate line scan[n] is set to HIGH, turning off the switching TFTs M2, M3. The control line em[n] is then set to LOW, turning on the switching TFTs M5, M6.
This renders the gate-to-source voltage of the driver TFT M1 Vda+Vth−VDD. When the gate-to-source voltage Vgs of the TFT M1 is less in absolute value than the drain-to-source voltage Vds, the current flow Ids through the TFT M1 is given by the following expression:
                    Ids        =                              k            ⁡                          (                              Vgs                -                Vth                            )                                2                                        =                              k            ⁡                          (                                                (                                      Vda                    +                    Vth                    -                    VDD                                    )                                -                Vth                            )                                2                                        =                              k            ⁡                          (                              Vda                -                VDD                            )                                2                                    where k is a constant, and Vth is positive. The current flow through the driver TFT M1 is therefore determined by the power supply line VDD and the voltage, Vda, on the data line data[m], regardless of the threshold voltage Vth of the driver TFT M1.        
The use of the pixel circuit in FIG. 40 in this manner also enables the current output level of the driver TFT M1 to be specified regardless of the threshold voltage of the driver TFT M1.
A desired current can be fed to the OLED by the use of the pixel circuit structure of FIG. 39 or FIG. 40 regardless of the threshold voltage of the driver TFT.
Inconveniences may however occur with these structures. In the pixel circuit structure in FIG. 39, each pixel includes four TFTs, two capacitors, and one OLED. For an amorphous silicon TFT, polysilicon TFT, or CG silicon TFT, the capacitors are each made up of either a silicon film and a gate electrode or a gate electrode and a source electrode. The capacitor's dielectric layer is made of a gate insulating film, which is an ordinary insulating film. The relative permittivity of the film is so low that the capacitor needs be large in area to provide necessary capacitance.
This capacitor size requirement in the pixel of the circuit structure in FIG. 39 places constraints on pixel size reduction. A required number of pixels may not be accommodated in a predetermined screen size. These problems can occur even with a top emission structure where emitted light is let out from the sealing film, opposite the TFT substrate.
The same description is applicable to the pixel circuit structure in FIG. 40. In the pixel circuit structure in FIG. 40, each pixel includes six TFTs, one capacitor, and one OLED.
The need for as many as six TFTs in the pixel places constraints on pixel size reduction. A required number of pixels may not be accommodated in a predetermined screen size. These problems can occur, again, even with a top emission structure.